Five Points On the Concepts!

Program Counter(PC) is the Current instruction address. Updated in every cycle(adding 1 if inst. is not a jump or branch).

PC ad address to fetch instruction from Instruction Memory.

Control Unit decode instruction(jump, assignment, branch, etc.) and control gen. Forward Data and Control signal to data memory and ALU(Arithmetic logic unit)

Processor

Princeton Architecture CPU comprises ALU and control unit.

Memory organization: Data are stored in row.

• One address for 1-byte data(=8 bits)

Instruction Set Design

Role: Bridge between Software and General-Purpose CPU. Performance evaluation: 1/execution time. CPI: cycle per instruction.

Factors:

• Inst. #:
  • ISA

Memory access:

• Register File:
  • inside CPU
  • access with index
  • access different registers at the same time
  • samll size, high access speed
• Main Memory:
  • outside CPU
  • access with addr.
  • can not access diff at the same time
  • Large size and low speed

In MIPS, 1 word = 4 bytes = 32 bits

ISA design: RISC(simpler) & CISC

Example:

• Assignment
• Branch
• Jump
• Return

ISA Design!

• call S2, fib; # s2 = return
• ret(urn) S2; #

Trade-Off